1. Field of the Invention
Generally, the present invention relates to the field of manufacturing integrated circuits, and, more particularly, to a semiconductor device, such as a field effect transistor, having an improved retrograde dopant profile in a channel region of the transistor element, and a method of manufacturing such a semiconductor device.
2. Description of the Related Art
Field effect transistors, such as MOS transistors, represent one of the most frequently used circuit elements in modern integrated circuits. Typically, a huge number of field effect transistors is simultaneously formed on an appropriate substrate and are connected to provide the required functionality of the circuit. Generally, a field effect transistor comprises two highly doped semiconductor regions, commonly silicon regions, that are also referred to as drain and source regions, and which are embedded in a lightly and inversely doped semiconductor region, the so-called N-well or P-well, depending on the type of transistor to be formed. The drain and source regions are spaced apart with a channel region interposed, wherein a conductive channel forms between the drain and source regions in the channel region upon application of an appropriate voltage to a gate electrode that is usually formed over the channel region and is separated therefrom by a gate insulation layer, often provided as a gate oxide layer.
As feature sizes of the individual semiconductor elements are steadily decreasing, for example, the distance between the source and drain regions (also referred to as the channel length) represents a critical dimension in this respect, device performance increases. However, these changes present new challenges to be overcome by process engineers so as to develop new processes and techniques compatible with the decreased feature sizes that do not partially offset the improvements obtained by decreasing the feature sizes. For instance, reducing the channel length generally requires the reduction of the thickness of the gate insulation layer so that the formation of the conductive channel remains sufficiently controllable by the applied gate voltage. Forming a gate insulation layer of a few nanometers in thickness, as is typical for sophisticated MOS transistors, therefore requires an advanced process technology to minimize any lattice damage in the semiconductor region underlying the gate insulation layer so as to allow formation of a high quality gate insulation layer, such as an oxide layer, for guaranteeing a high degree of reliability of the device over the whole operating life. Moreover, only a relatively intact semiconductor region allows the formation of a gate insulation layer having a relatively smooth interface with the semiconductor material so that scattering events of charge carriers are minimized.
A reduction of the channel length in modern devices leads to an improved conductivity. However, in some cases, it may be desirable to further improve the conductivity by enhancing carrier mobility in the channel region without excessively decreasing the channel length. Accordingly, in modern devices, a so-called retrograde channel doping profile is contemplated. As is well known, dopant atoms in the semiconductor lattice may represent scattering centers for charge carriers moving under the influence of an electrical field prevailing in the semiconductor region. Therefore, in modern devices, the retrograde channel dopant profile may be used, that is, the concentration of dopants increases from the gate insulation layer to the areas located deeper down the channel region, so that charge carriers forming the conductive channel essentially in the vicinity of the gate insulation layer encounter a relatively low concentration of scattering centers so that the overall conductivity in the channel is enhanced. A retrograde channel dopant profile, however, is very difficult to obtain as will be detailed in the following by referring to FIGS. 1a-1c and FIGS. 2a-2b. 
FIG. 1a shows a schematic cross-sectional view of a semiconductor element 100 at an early manufacturing stage. The semiconductor element 100 is illustrated in this example as a complementary MOS transistor pair, wherein a semiconductor region 101, such as a silicon region, a shallow trench isolation 102, for example comprising silicon dioxide, is formed to separate an N-well structure 120 and a P-well structure 110. In the N-well structure 120, implanted, i.e., doped, portions are indicated by 121, 122, 123 and 124, and correspondingly, in the P-well structure 110, implanted portions 111, 112, 113 and 114 are illustrated. The implantation portions 111, 121 located lowest in the N-well structure 120 and the P-well structure 110 are also referred to as buried implants. The implanted portions 112, 122 are commonly known as fill implants, whereas the implanted portions 113, 123 are usually referred to as punch-through implants. The implanted portions 114, 124 are also called VT implants, wherein VT indicates the threshold voltage of the transistor elements to be formed.
A typical process flow for forming the semiconductor device 100 shown in FIG. 1a may comprise the following steps. First, the shallow trench isolation 102 is formed by photolithography, etching and deposition techniques that are well known in the art. Thereafter, the P-well structure 110 and the N-well structure 120 are defined by sequentially performed ion implantation processes, wherein, prior to the actual implantation process, a sacrificial layer, such as an oxide layer (not shown), may be deposited over the semiconductor region 101 to more precisely control the implantation process. For defining the N-well structure 120, typically phosphorous or arsenic ions are used, whereas for defining the P-well structure 110, typically boron ions are employed. During implantation, the dose and the energy of the respective implantation process is controlled so as to locate the peak concentration of the corresponding ion species in the respective implantation portions 121 to 124 and 111 to 114. It should be noted that due to the nature of the implantation process, the boundaries of the implantation portions for defining the P-well structure 110 and the N-well structure 120 are not sharp boundaries as shown in FIG. 1a but, instead, have gradual transitions.
FIG. 2a is a graph, in which the dopant concentration of the N-well structure 120 and the P-well structure 110 is depicted with respect to the depth in the respective well structures. In particular, it is evident from FIG. 2a that the VT implantation (114, 124), indicated by the same reference number as the respective implantation portions, leads to a dopant concentration that significantly decreases at the vicinity of the surface of the semiconductor device 100. That is, the dopant concentration immediately after the implantation process exhibits a desired retrograde dopant profile in the N-well structure 120 and the P-well structure 110 near the surface of the semiconductor device 100, where, after completion of the device, a channel will form during operation of the device.
After defining the P-well structure 110 and the N-well structure 120 by ion implantation, the semiconductor device 100 has to be subjected to a heat treatment so as to activate the implanted ions, that is, to locate the majority of the ions at lattice sites, and to cure any lattice damage caused by the ion bombardment. Unfortunately, during this heat treatment, an inevitable diffusion takes place and the boundaries between the respective implantation portions will smear out more intensively so that the vertical dopant profile within the P-well structure 110 and the N-well structure 120 will become more indefinite.
FIG. 2b shows a corresponding graph with a typical dopant profile with respect to the depth of the respective well structure. Due to the up-diffusion of the dopant atoms during the heat treatment, the initially retrograde profile in the vicinity of the surface of the semiconductor device 100, as indicated by reference number 200, may have become substantially uniformly distributed.
FIG. 1b schematically shows the semiconductor device 100 in an advanced manufacturing stage. In FIG. 1b, the semiconductor device 100 comprises within the P-well structure 110 heavily N-doped source and drain regions 131, including lightly doped extensions 132. In the N-well structure 120, similarly, heavily P-doped source and drain regions 141, including lightly doped extensions 142, are provided. A gate insulation layer 135, for example, a gate oxide layer, is provided on the entire surface of the semiconductor device 100 to separate a gate electrode 134 from a corresponding channel region 136 and a gate electrode 144 from the corresponding channel region 146. Spacer elements 133 are provided at the sidewalls of the gate electrode 134 and respective spacer elements 143 are located at the sidewalls of the gate electrode 144. Thus, the semiconductor device 100 includes an N-channel transistor 130 and a P-channel transistor 140.
Typically, the N-channel transistor 130 and the P-channel transistor 140 are formed by the following processes. After the heat treatment, the gate insulation layer 135 is formed, wherein the gate insulation layer may be deposited by chemical vapor deposition (CVD), or, if an oxide layer is used, a rapid thermal furnace process or a conventional furnace oxidation process may be used. Since, commonly, elevated temperatures are involved in fabricating the gate insulation layer 135, this process also contributes to a further diffusion of the dopants within the P-well structure 110 and the N-well structure 120. Thereafter, polysilicon is deposited and patterned by sophisticated photolithography techniques to form the gate electrodes 134 and 144. With a first implantation, the extensions 132 and 142 are defined, and, subsequently, the spacer elements 133, 143 are formed and serve as an implantation mask during a subsequent implantation process for defining the source and drain regions 131, 141. Since a further heat treatment is necessary to activate the dopants within the regions 131, 132 and 141, 142 and to cure any crystal damage caused by the preceding implantation steps, the initial dopant concentration, as shown in FIG. 2a, will be even more strongly affected so that, after the plurality of heat treatments, the actual dopant concentration will be represented by the graph shown in FIG. 2b. In particular, it is thus very difficult to obtain or to maintain a retrograde dopant profile in the channel regions 136 and 146, which would be desirable to achieve an improved carrier mobility therein.
According to the difficulties involved in obtaining or maintaining a retrograde dopant profile in the channel region of a field effect transistor caused by the conventional process flow, there is a strong need for an improved method for forming semiconductor devices exhibiting a retrograde dopant profile.